Table 3a. AUXR: Auxiliary Register
AUXR
Address = 8EH
Not Bit Addressable
–
–
Bit
7
6
–
WDIDLE DISRTO
5
4
3
Reset Value = XXX00X00B
–
EXTRAM DISALE
2
1
0
–
DISALE
EXTRAM
DISTRO
WDIDLE
Reserved for future expansion
Disable/Enable ALE
DISALE
Operating Mode
0
ALE is emitted at a constant rate of 1/6 the oscillator frequency
1
ALE is active only during a MOVX or MOVC instruction
Internal External RAM (00H-FFH) access using MOVX @ Ri/DPTR
EXTRAM Operating Mode
0
Internal ERAM (00H-FFH) access using MOVX @ Ri/DPTR
1
External data memory access
Disable/Enable Reset out
DISRTO
0
Reset pin is driven High after WDT times out
1
Reset pin is input only
Disable/Enable WDT in IDLE mode
WDIDLE
0
WDT continues to count in IDLE mode
1
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both
internal and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in
SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The
user should always initialize the DPS bit to the appropriate
Table 3b. AUXR1: Auxiliary Register 1
value before accessing the respective Data Pointer Regis-
ter.
Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.
AUXR1
Address = A2H
Reset Value = XXXXXXX0B
Not Bit Addressable
–
–
–
–
–
–
–
DPS
Bit
7
6
5
4
3
2
1
0
–
DPS
6
Reserved for future expansion
Data Pointer Register Select
DPS
0
Selects DPTR Registers DP0L, DP0H
1
Selects DPTR Registers DP1L, DP1H
AT87F51RC