AT87F51RC-12AC データシートの表示（PDF） - Atmel Corporation
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AT87F51RC-12AC Datasheet PDF : 25 Pages
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AT87F51RC
Memory Organization
MCS-51 devices have a separate address space for Pro-
gram and Data Memory. Up to 64K bytes each of external
Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are
directed to external memory.
On the AT87F51RC, if EA is connected to VCC, program
fetches to addresses 0000H through 7FFFH are directed to
internal memory and fetches to addresses 8000H through
FFFFH are to external memory.
Data Memory
The AT87F51RC has internal data memory that is mapped
into four separate segments: the lower 128 bytes of RAM,
upper 128 bytes of RAM, 128 bytes special function regis-
ter (SFR) and 256 bytes expanded RAM (ERAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to
7FH) are directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80H to
FFH) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses
80H to FFH) are directly addressable only.
4. The 256-byte expanded RAM (ERAM, 00H-FFH) is
indirectly accessed by MOVX instructions, and with
the EXTRAM bit cleared.
The Lower 128 bytes can be accessed by either direct or
indirect addressing. The Upper 128 bytes can be accessed
by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. This means they
have the same address, but are physically separate from
the SFR space.
When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to the
upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction. Instructions that
use direct addressing access SFR space. For example:
MOV 0A0H, # data
accesses the SFR at location 0S0H (which is P2). Instruc-
tions that use indirect addressing access the Upper 128
bytes of data RAM. For example:
MOV@R0, # data
where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
The 256 bytes of ERAM can be accessed by indirect
addressing, with EXTRAM bit cleared and MOVX instruc-
tions. This part of memory is physically located on-chip,
logically occupying the first 256 bytes of external data
memory.
Figure 1. Internal and External Data Memory Address
(with EXTRAM = 0)
FF
ERAM
256 BYTES
00
FF
UPPER
128 BYTES
INTERNAL
RAM
80
LOWER
128 BYTES
INTERNAL
RAM
00
FF
SPECIAL
FUNCTION
REGISTER
FF
EXTERNAL
DATA
MEMORY
80
0100
0000
With EXTRAM = 0, the ERAM is indirectly addressed,
using the MOVX instruction in combination with any of the
registers R0, R1 of the selected bank or DPTR. An access
to ERAM will not affect ports P0, P2, P3.6 (WR), and P3.7
(RD). For example, with EXTRAM = 0,
MOVX@R0, # data
where R0 contains 0A0H, accesses the ERAM at address
0A0H rather than external memory. An access to external
data memory locations higher than FFH (i.e. 0100H to
FFFFH) will be performed with the MOVX DPTR instruc-
tions in the same way as in the standard MCS-51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as
write and read timing signals. Refer to Figure 1.
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be
similar to the standard MCS-51. MOVX@Ri will provide an
8-bit address multiplexed with data on Port 0 and any out-
put port pins can be used to output higher-order address
bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 out-
puts the high-order 8 address bits (the contents of DP0H),
while Port 0 multiplexes the low-order 8 address bits (the
contents of DP0L) with data. MOVX@Ri and
MOVX@DPTR will generate either read or write signals on
P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256
bytes RAM (lower and upper RAM) internal data memory.
The stack may not be located in the ERAM.
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