AT89C51RB2-3CSUM データシートの表示（PDF） - Atmel Corporation

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AT89C51RB2-3CSUM

8-bit Microcontroller with 16K/32K Bytes Flash

Atmel Corporation 

Table 15. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

6

5

4

3

2

1

0

-

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

7

Bit

Mnemonic Description

Reserved

Watchdog Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

6

WDX2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

5

PCAX2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

4

SIX2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer 2 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

3

T2X2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer 1 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

2

T1X2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer0 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

1

T0X2 has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

CPU Clock

Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU

0

X2

and all the peripherals. Set to select 6 clock periods per machine cycle (X2

mode) and to enable the individual peripherals’X2’ bits. Programmed by

hardware after Power-up regarding Hardware Security Byte (HSB), Default

setting, X2 is cleared.

Reset Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)

Not bit addressable

18 AT89C51RB2/RC2

4180E–8051–10/06

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