AT89LS51(1997) データシートの表示（PDF） - Atmel Corporation
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AT89LS51 Datasheet PDF : 16 Pages
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Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 2.7V to 6V; Load Capacitance = 80 pF)
Symbol Parameter
12 MHz Osc
Variable Oscillator
Min
Max
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
tQVXH
Output Data Setup to Clock Rising Edge
700
tXHQX
Output Data Hold After Clock Rising Edge
50
tXHDX
Input Data Hold After Clock Rising Edge
0
tXHDV
Clock Rising Edge to Input Data Valid
12tCLCL
10tCLCL-133
2tCLCL-117
0
700
10t CLCL-133
Units
µs
ns
ns
ns
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
CLOCK
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
INPUT DATA
0
1
2
3
4
5
6
7
8
tXLXL
tQVXH
0
tXHDV
VALID
tXHQX
1
2
tXHDX
VALID
VALID
3
VALID
4
VALID
5
VALID
6
7
SET TI
VALID
VALID
SET RI
AC Testing Input/Output Waveforms (1) Float Waveforms (1)
VCC - 0.5V
0.45V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
VLOAD
V
+
LOAD
0.1V
V LOAD - 0.1V
Timing Reference
Points
V OL - 0.1V
V OL + 0.1V
Note:
1. AC inputs during testing are driven at 2.4V for a
logic “1” and 0.45V for a logic “0”. Timing measure-
ments are made at 2.0V for a logic “1” and 0.8V for a
logic “0”.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
4-58
Not
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