AT89S8252(2000) データシートの表示（PDF） - Atmel Corporation
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AT89S8252 Datasheet PDF : 34 Pages
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AT89S8252
Programming the Flash and EEPROM
Atmel’s AT89S8252 Flash Microcontroller offers 8K bytes
of in-system reprogrammable Flash Code memory and 2K
bytes of EEPROM Data memory.
The AT89S8252 is normally shipped with the on-chip Flash
Code and EEPROM Data memory arrays in the erased
state (i.e. contents = FFH) and ready to be programmed.
This device supports a High-voltage (12V) Parallel pro-
gramming mode and a Low-voltage (5V) Serial
programming mode. The serial programming mode pro-
vides a convenient way to download the AT89S8252 inside
the user’s system. The parallel programming mode is com-
patible with conventional third party Flash or EPROM
programmers.
The Code and Data memory arrays are mapped via sepa-
rate address spaces in the serial programming mode. In
the parallel programming mode, the two arrays occupy one
contiguous address space: 0000H to 1FFFH for the Code
array and 2000H to 27FFH for the Data array.
The Code and Data memory arrays on the AT89S8252 are
programmed byte-by-byte in either programming mode. An
auto-erase cycle is provided with the self-timed program-
ming operation in the serial programming mode. There is
no need to perform the Chip Erase operation to reprogram
any memory location in the serial programming mode
unless any of the lock bits have been programmed.
In the parallel programming mode, there is no auto-erase
cycle. To reprogram any non-blank byte, the user needs to
use the Chip Erase operation first to erase both arrays.
Parallel Programming Algorithm: To program and verify
the AT89S8252 in the parallel programming mode, the fol-
lowing sequence is recommended:
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait
for at least 10 milliseconds.
2. Set PSEN pin to “L”
ALE pin to “H”
EA pin to “H” and all other pins to “H”.
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P2.6, P2.7, P3.6, P3.7 to select one of
the programming operations shown in the Flash
Programming Modes table.
4. Apply the desired byte address to pins P1.0 to P1.7
and P2.0 to P2.5.
Apply data to pins P0.0 to P0.7 for Write Code
operation.
5. Raise EA/VPP to 12V to enable Flash programming,
erase or verification.
6. Pulse ALE/PROG once to program a byte in the
Code memory array, the Data memory array or the
lock bits. The byte-write cycle is self-timed and typi-
cally takes 1.5 ms.
7. To verify the byte just programmed, bring pin P2.7 to
“L” and read the programmed data at pins P0.0 to
P0.7.
8. Repeat steps 3 through 7 changing the address and
data for the entire 2K or 8K bytes array or until the
end of the object file is reached.
9. Power-off sequence:
Set XTAL1 to “L”.
Set RST and EA pins to “L”.
Turn VCC power off.
In the parallel programming mode, there is no auto-erase
cycle and to reprogram any non-blank byte, the user needs
to use the Chip Erase operation first to erase both arrays.
Data Polling: The AT89S8252 features DATA Polling to
indicate the end of a write cycle. During a write cycle in the
parallel or serial programming mode, an attempted read of
the last byte written will result in the complement of the writ-
ten datum on P0.7 (parallel mode), and on the MSB of the
serial output byte on MISO (serial mode). Once the write
cycle has been completed, true data are valid on all out-
puts, and the next cycle may begin. DATA Polling may
begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming in the
parallel programming mode can also be monitored by the
RDY/BSY output signal. Pin P3.4 is pulled Low after ALE
goes High during programming to indicate BUSY. P3.4 is
pulled High again when programming is done to indicate
READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed Code or Data byte can be
read back via the address and data lines for verification.
The state of the lock bits can also be verified directly in the
parallel programming mode. In the serial programming
mode, the state of the lock bits can only be verified indi-
rectly by observing that the lock bit features are enabled.
Chip Erase: Both Flash and EEPROM arrays are erased
electrically at the same time. In the parallel programming
mode, chip erase is initiated by using the proper combina-
tion of control signals and by holding ALE/PROG low for 10
ms. The Code and Data arrays are written with all “1”s in
the Chip Erase operation.
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