AT89S852-12PC データシートの表示（PDF） - Atmel Corporation

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AT89S852-12PC

8 bit Microcontroller with 8K bytes Flash

Atmel Corporation 

Program Memory Lock Bits

The AT89S8252 has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the ad-

ditional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA

pin is sampled and latched during reset. If the device is

powered up without a reset, the latch initializes to a ran-

dom value and

Lock Bit Protection Modes (1, 2)

holds that value until reset is activated. The latched value

of EA must agree with the current logic level at that pin in

order for the device to function properly.

Once programmed, the lock bits can only be unpro-

grammed with the Chip Erase operations in either the par-

allel or serial modes.

Program Lock Bits

LB1 LB2 LB3 Protection Type

1

U

U

U No internal memory lock feature.

MOVC instructions executed from external program memory are disabled from

2

P

U

U fetching code bytes from internal memory. EA is sampled and latched on reset and

further programming of the Flash memory (parallel or serial mode) is disabled.

3

P

P

U Same as mode 2, but parallel or serial verify are also disabled.

4

P

P

P Same as mode 3, but external execution is also disabled.

Notes: 1. U = Unprogrammed.

2. P = Programmed.

Programming the Flash and EEPROM

Atmel’s AT89S8252 Flash Microcontroller offers 8K bytes

of in-system reprogrammable flash PEROM Code mem-

ory and 2K bytes of EEPROM Data memory.

The AT89S8252 is normally shipped with the on-chip

PEROM Code and EEPROM Data memory arrays in the

erased state (i.e. contents = FFH) and ready to be pro-

grammed. This device supports a High-Voltage (12V) Par-

allel programming mode and a Low-Voltage Serial pro-

gramming mode. The serial programming mode provides

a convenient way to download the AT89S8252 inside the

user’s system. The parallel programming mode is compat-

ible with conventional third party Flash or EPROM pro-

grammers.

The Code and Data memory arrays are mapped via sepa-

rate address spaces in the serial programming mode. In

the parallel programming mode, the two arrays occupy

one contiguous address space: 0000H to 1FFFH for the

Code array and 2000H to 27FFH for the Data array.

The Code and Data memory arrays on the AT89S8252 are

programmed byte-by-byte in either programming modes.

An auto-erase cycle is provided with the self-timed pro-

gramming operation in the serial programming mode.

There is no need to perform the Chip Erase operation to

reprogram any memory location in the serial programming

mode.

In the parallel programming mode, there is no auto-erase

cycle and to reprogram any non-blank byte, the user

needs to use the Chip Erase operation first to erase both

arrays.

Parallel Programming Algorithm

To program and verify the AT89S8252 in the parallel pro-

gramming mode, the following sequence is recom-

mended:

1. Power-up sequence:

Apply power between VCC and GND pins with all other

pins floating.

Set RST pin to ’H’.

Apply a 4 MHz to 24 MHz clock to XTAL1 pin and wait

for

at least 10 milliseconds.

2. Set PSEN pin to ’H’

ALE pin to ’H’

EA pin to ’H’ and all other pins to ’H’.

3. Apply the appropriate combination of ’H’ or ’L’ logic lev-

els to pins P2.6, P2.7, P3.6, P3.7 to select one of the

programming operations shown in the PEROM Pro-

gramming Modes table.

4. Apply the desired byte address to pins P1.0 to P1.7

and P2.0 to P2.5.

Apply data to pins P0.0 to P0.7 for Write Code operation.

5. Raise EA/VPP to 12V to enable Flash programming,

erase or verification.

6. Pulse ALE/PROG once to program a byte in the Code

memory array, the Data memory array or the lock

bits. The byte-write cycle is self-timed and typically

takes 1.5 ms.

(continued)

18

AT89S8252

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