ATF1504BE データシートの表示（PDF） - Atmel Corporation

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ATF1504BE

High-performance CPLD

Atmel Corporation 

ATF1504BE

6. JTAG-BST/ISP Overview

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the

ATF1504BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-

tained in a boundary-scan cell) adjacent to each component so that signals at component

boundaries can be controlled and observed using scan testing methods. Each input pin and I/O

pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller

is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRE-

LOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504BE’s BSC can be fully described

using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1504BE testing to be

described and implemented using any one of the third-party development tools supporting this

standard.

The ATF1504BE also has the option of using the four JTAG-standard I/O pins for ISP. The

ATF1504BE is programmable through the four JTAG pins using the IEEE standard JTAG pro-

gramming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level

programming signals from the ISP interface for in-system programming. The JTAG feature is a

programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are

available as I/O pins.

6.1 JTAG Boundary-scan Cell (BSC) Testing

The ATF1504BE contains 64 I/O pins and four dedicated input pins. Each input pin and I/O pin

has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in

detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers

and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one

for the macrocells. The BSCs in the device are chained together through the capture registers.

Input to the capture register chain is fed in from the TDI pin while the output is directed to the

TDO pin. Capture registers are used to capture active device data signals, to shift data in and

out of the device and to load data into the update registers. Control signals are generated inter-

nally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and

macrocells is shown below.

Figure 6-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)

3637B–PLD–1/08

Note: The ATF1504BE has a pull-up option on TMS and TDI pins. This feature is selected as a design

option.

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