ATF1516SE-10 データシートの表示（PDF） - Atmel Corporation

部品番号

コンポーネント説明

メーカー

ATF1516SE-10

ATF15xxSE Family Datasheet

Atmel Corporation 

JTAG-BST

Overview

ATF15xxSE Family

The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP)

controller. The boundary-scan technique involves the inclusion of a shift-register stage (con-

tained in a boundary-scan cell) adjacent to each component so that signals at component

boundaries can be controlled and observed using scan testing principles. Each input pin and

I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The

ATF15xxSE Family does not currently include a Test Reset (TRST) input pin because the TAP

controller is automatically reset at power-up. The ATF15xxSE Family implements six BST

instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx

Family BST and ISP instructions have a length of 10 bits.

JTAG BST Instructions

SAMPLE/PRELOAD

EXTEST

BYPASS

IDCODE

UESCODE

HIGHZ

7 ISP instructions

Description

Captures signals at the device pins for later examination,

or loads a data pattern prior to an EXTEST instruction.

Allows testing of off-chip circuitry and interconnections

by forcing a pattern on the output pins or capturing

signals from the input pins.

Places a single shift register stage between TDI and

TDO, allowing test BST data to pass through a particular

device in a chain of devices.

Places the 32-bit IDCODE register between TDI and

TDO, allowing the IDCODE data to be shifted out of

TDO.

Places the 16-bit user electronic signature register

between TDI and TDO, allowing the UESCODE data to

be shifted out of TDO.

Places the BYPASS register between TDI and TDO in a

high impedance mode, protecting the device from

damage from externally applied test signals.

These seven instructions allow in-system programming

via the four JTAG pins.

The ATF15xxSE Family BST implementation complies with the Boundary-scan Definition Lan-

guage (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party

tool that supports the BSDL format can be used to perform BST on the ATF15xxSE Family.

The ATF15xxSE Family also has the option of using four JTAG-standard I/O pins for in-system

programming (ISP). The ATF15xxSE Family is programmable through the four JTAG pins

using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is per-

formed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG

feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG

control pins are available as I/O pins. Refer to Atmel Application Note “Designing for In-Sys-

tem Programmability with Atmel CPLDs for more details.

11

2401D–PLD–09/02

Share Link: