ATMEGA6450-16AI(2004) データシートの表示（PDF） - Atmel Corporation
部品番号
コンポーネント説明
メーカー
ATMEGA6450-16AI Datasheet PDF : 347 Pages
| |||
SRAM Data Memory
Figure 10 shows how the ATmega325/3250/645/6450 SRAM Memory is organized.
The ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units
than can be supported within the 64 locations reserved in the Opcode for the IN and
OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 2304/4352 data memory locations address both the Register File, the I/O
memory, Extended I/O memory, and the internal data SRAM. The first 32 locations
address the Register File, the next 64 location the standard I/O memory, then 160 loca-
tions of Extended I/O memory, and the next 2048/4096 locations address the internal
data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Regis-
ters, and the 2,048 bytes of internal data SRAM in the ATmega325/3250/645/6450 are
all accessible through all these addressing modes. The Register File is described in
“General Purpose Register File” on page 12.
Figure 10. Data Memory Map
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(2048 x 8)/
(4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
0x08FF/0x10FF
Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clkCPU cycles as described in Figure
11.
18 ATmega325/3250/645/6450
2570A–AVR–09/04
Share Link: 