ATMEGA6450-16AI(2004) データシートの表示（PDF） - Atmel Corporation
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ATMEGA6450-16AI Datasheet PDF : 347 Pages
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Switching Time
Table 13. Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occur in the clock system and that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock fre-
quency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to
determine the state of the prescaler – even if it were readable, and the exact time it
takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2
before the new clock frequency is active. In this interval, 2 active clock edges are pro-
duced. Here, T1 is the previous clock period, and T2 is the period corresponding to the
new prescaler setting.
32 ATmega325/3250/645/6450
2570A–AVR–09/04
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