LB1921 データシートの表示（PDF） - SANYO -> Panasonic
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LB1921 Datasheet PDF : 10 Pages
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LB1921
This section describes the LB1921 and the external components used.
1. Speed Control Circuit
This IC uses the combination of a speed discriminator circuit and a PLL circuit for speed control. The speed
discriminator circuit outputs an error signal once every two FG periods using a charge pump technique. The PLL
circuit outputs a phase error signal once every FG period, also using a charge pump technique. As compared to earlier
schemes that only used a speed discriminator, the combination of a PLL circuit with a speed discriminator provides
improved speed variation suppression when using a motor with large load variations. Since the following formula
determines the FG servo frequency, the motor speed must be set using the number of FG pulses and the crystal
oscillator frequency.
fFG (servo) = fOSC/8192
fOSC: crystal oscillator frequency
2. Direct PWM Drive
This IC adopts direct PWM drive to minimize power loss in the output. The output transistors are always saturated
when on and the motor drive power is adjusted by changing the output on duty. Since output switching is performed
by the lower side transistor, the three Schottky diodes D1, D2 and D3 must be inserted between OUT and VCC. (Note
that a through current will flow at the instant the lower side transistor turns on if these diodes do not have a short
reverse recovery time.) Normal rectifying diodes can be used for the diodes between OUT and ground.
3. Current Control Circuit
The current control circuit applies current control at a current determined by the relation I = 0.5/Rf, i.e. peak current
limitation. The control operation reduces the output on duty and thus suppresses the current. No phase compensation
capacitor is required.
4. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed and the LD pin goes low when the motor is in the lock range.
(This pin is an open-collector output.) When the motor speed goes out of the lock range, the LB1921 changes the
motor drive output on duty according to the speed error to control the motor speed to be within the lock range.
5. PWM Frequency
The PWM frequency is determined by the resistor and capacitor (R3 and C6) connected to the CR pin.
• When R3 is connected to the 4-V fixed voltage supply
fPWM ≈ 1/(1.2 × C × R)
• When R3 is connected to the 7-V fixed voltage supply
fPWM ≈ 1/(0.5 × C × R)
R3 should not be any smaller than 30 kΩ. A PWM frequency of about 15 kHz is desirable. If the PWM frequency is
too low the motor will vibrate at the PWM frequency when the motor is restrained causing disturbing audible noise.
Inversely, switching loss increases if the PWM frequency is too high.
6. Ground Leading
GND1 (pin 22) is the ground for circuits other than the output block.
GND2 (pin 11) is the ground for the output block (emitters of the sink transistors).
D4, D5 and D6 are connected to GND2. All other external components are connected to GND1. The GND1 and
GND2 lines are connected to a single ground point at the connector. Since GND2 carries large currents, it should be
kept as short as possible.
7. Output Parasitic Effects
Parasitic effects occur when the output pin voltage falls –0.7 V (this value decreases as the temperature increases)
below the GND1 and GND2 voltage. Similarly, the output pin voltage should not be allowed to exceed VCC by more
than 1 V. When parasitism occurs, initially speed control is lost intermittently, but if the amount of parasitism
increases the output transistors can be destroyed. Schottky diodes with a small Vf are used for D1, D2 and D3 to
prevent through currents. As a result, the potential difference between the output pins and VCC is not that much of a
problem. Although normal rectifying diodes can be used for D4, D5 and D6, the printed circuit board pattern must be
kept as short as possible (as recommended in item 6) to prevent parasitism from occurring.
No. 5439-7/10
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