BD9270F データシートの表示（PDF） - ROHM Semiconductor
部品番号
コンポーネント説明
メーカー
BD9270F Datasheet PDF : 5 Pages
| |||
4/4
〇NOTE FOR USE
１. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum
ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode.
Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond
the expected absolute maximum ratings.
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within
recommended operating range. The standard electrical characteristic values cannot be guaranteed at other
voltages in the operating ranges, however the variation will be small.
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL Pin Voltage should be under
VCC voltage +0.3V even if the voltage is under each terminal ratings.
６. BD9270F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD
circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect
the IC or guarantee its operation of the thermal shutdown circuit is assumed.
７. When modifying the external circuit components, make sure to leave an adequate margin for external components
actual value and tolerance as well as dispersion of the IC.
８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
９. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 1.5V), It does not operate Timer Latch.
11. By STB voltage, BD9270F are changed to 2 states. Therefore, do not input STB pin voltage between one state
and the other state (0.8～2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N
junction is formed from this P layer of each pin. For example, the relation between each potential is as
follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result
in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must
not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P
substrate) voltage to an input pin.
Resistance
(PinA)
P＋
Ｎ
P
P＋
N
P substrate
GND
Parasitic diode
Transistor (NPN)
(PinB)
B
CＣ
E
N
GND
N
N
Ｎ
P substrate
GND
Parasitic diode
(PinB)
(PinA)
Parasitic diode
B ＢC Ｃ
EＥ
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. B
Share Link: 