SY89809LTHTR(2005) データシートの表示（PDF） - Micrel
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SY89809LTHTR Datasheet PDF : 7 Pages
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Micrel, Inc.
Precision Edge®
SY89809L
PACKAGE/ORDERING INFORMATION
VCCI
HSTL_CLK
/HSTL_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GND
OE
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
Top View
21
5
TQFP
T32-1
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Ordering Information(1)
VCCO
Q3
/Q3
Q4
/Q4
Q5
/Q5
VCCO
Part Number
SY89809LTC
SY89809LTCTR(2)
SY89809LTH(3)
Package
Type
T32-1
T32-1
T32-1
SY89809LTHTR(2, 3) T32-1
Operating
Range
Package
Marking
Lead
Finish
Industrial
SY89809LTC
Sn-Pb
Industrial
SY89809LTC
Sn-Pb
Industrial
SY89809LTH with NiPdAu
Pb-Free bar line indicator Pb-Free
Industrial
SY89809LTH with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
PIN DESCRIPTION
Pin Number
2, 3
Pin Name
HSTL_CLK,
/HSTL_CLK
5, 6
LVPECL_CLK,
/LVPECL_CLK
4
CLK_SEL
8
OE
Type
HSTL
Input
LVPECL
Input
LVTTL
Input
LVTTL
Input
31, 29, 27, 23,
21, 19, 15, 13,
11
30, 28, 26, 22,
20, 18, 14, 12,
10
1
9, 16, 17, 24,
25, 32
7
Q0–Q8
/Q0–/Q8
VCCI
VCCO
GND
HSTL
Output
HSTL
Output
VCC Core
Power
VCC Output
Power
Ground
Pin Function
Differential clock input selected by CLK_SEL. Can be left floating if not
selected. Floating input, if selected produces an indeterminate output. HSTL
input signal requires external termination 50Ω to GND.
Differential clock input selected by CLK_SEL. Can be left floating. Floating
input, if selected produces a LOW at the output (internal 75Ω pull-downs).
Requires external termination. 75kΩ pull-up.
Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.
11kΩ pull-up.
Enable input synchronized internally to prevent glitching of the Q0-Q8 and
/Q0-/Q8 outputs. Must be a minimum of three clock periods wide if
synchronous with the CLK inputs and must meet the tS and tH requirements
(refer to AC Electrical Characteristics). If asynchronous, must be a minimum
of four clock periods wide. 11kΩ pull-up.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50Ω to GND. Q0–Q8 outputs are static LOW when OE = LOW. Unused
output pairs may be left floating.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50Ω to GND. /Q0–/Q8 outputs are static HIGH when OE = LOW.
Unused output pairs may be left floating.
Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallel with
0.01µF low ESR capacitors as close to VCCI pin as possible.
Output Buffer VCC connected to 1.8V supply. Bypass with 0.1µF in parallel
with 0.01µF low ESR capacitors as close to VCCO pins as possible. All VCCO
pins should be connected together on the PCB.
Ground.
M9999-092005
hbwhelp@micrel.com or (408) 955-1690
2
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