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AS4LC1M16S1(2000) データシートの表示(PDF) - Alliance Semiconductor
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AS4LC1M16S1
(Rev.:2000)
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM
Alliance Semiconductor
AS4LC1M16S1 Datasheet PDF : 28 Pages
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AS4LC2M8S1
AS4LC1M16S1
AC parameters common to all waveforms
CAS
–7
Sym
Parameter
latency Min Max
3
–
5.5
t
AC
CLK to valid output delay 2
–
8.5
1
–
18
t
AH
Address hold time
t
AS
Address setup time
t
BDL
Last data-in to burst stop
Read/write command to
t
CCD
read/write command
–
1
2
–
0
–
1
–
t
CDL
Last data-in to new
column address delay
1
–
t
CH
CLK high-level width
2.75 –
3
7 1000
t
CK
CLK cycle time
2 8.7 1000
1 20 1000
t
CKED
CKE to CLOCK disable or
power-down entry mode
1
–
t
CKH
CKE hold time
t
CKS
CKE setup time
t
CL
CLK low-level width
CS, RAS, CAS, WE, DQM
t
CMH
hold time
1
–
2
–
2.75 –
1
–
t
CMS
CS, RAS, CAS, WE, DQM
setup time
2
–
t
DAL
Data-in to ACTIVE
command
3
5
–
2
5
–
1
4
–
t
DH
Data in hold time
t
DPL
Data in to PRECHARGE
t
DQD
DQM to input data delay
DQM to data mask during
t
DQM
writes
1
–
2
–
1
–
0
–
t
DQZ
DQM to data high Z
during reads
2
–
t
DS
Data in setup time
t
DWD
Write command to input
data delay
2
–
0
–
3
–
5.5
t
HZ
Data-out high-impedance
time
2
–
8.5
1
–
18
t
LZ
Data-out low-impedance
time
1
–
–8
Min Max
–
6
–
7
–
22
–
1
2
–
0
–
1
–
1
–
3
–
8
1000
10
1000
25
1000
1
–
1
–
2
–
3
–
1
–
2
–
5
–
5
–
4
–
1
–
2
–
1
–
0
–
2
–
2
–
0
–
–
6
–
9
–
22
1
–
–10
Min
Max Unit Notes
–
6
ns
6
–
6
ns 6,8
–
22 ns 6,8
–
1
ns
7
2
–
ns
7
0
–
t
CK
9
1
–
t
CK
9
1
–
t
CK
9
3
–
ns
7
10
1000 ns
10
12
1000 ns
10
25
1000 ns
10
1
–
t
CK
1
–
ns
2
–
ns
3.5
–
ns
7
1
–
ns
2
–
ns
5
–
t
CK
5,11
5
–
t
CK
5,11
4
–
t
CK
5,11
1
–
ns
2
–
t
CK
12
1
–
t
CK
9
0
–
t
CK
9
2
–
t
CK
9
2
–
ns
0
–
t
CK
9
–
9
ns
13
–
9
ns
13
–
22
ns
13
1
–
ns
8
ALLIANCE SEMICONDUCTOR
7/5/00
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