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PDM34078SA10QTY データシートの表示(PDF) - Paradigm Technology
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PDM34078SA10QTY
3.3V 32K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register
Paradigm Technology
PDM34078SA10QTY Datasheet PDF : 14 Pages
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PDM34078
Read/Write Timing Diagram
tCYC
CLK
ADSP
tADSH
ADSC
ADDRESS
ADV
BWE
BW4
-
BW1
CE
OE
tADSS
tCL
tAS
A1
tAH
tCEH
tCES
DATA
IN
DATA
OUT
tCQ
tCQX
tCH
A2
A3
tDH
tDS
Q1
A1
D1
A2
tOHZ
tOLZ
Q1
A2
Q2
A2
Q3
A3
NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is
high, CE2 is high and CE2 is low.
2. GW is high.
12
Rev 1.0 - 5/01/98
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