PDM34089SA10QITY データシートの表示（PDF） - Paradigm Technology

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PDM34089SA10QITY

3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter

Paradigm Technology 

PRELIMINARY

PDM34089

Sleep Mode Timing Diagram

CLK

ADSP

ADSC

SNOOZE

ZZ

tZZS

tZZREC

NOTES: 1. Data retention is guaranteed when ZZ is asserted and clock remains active.

2. ADSC and ADSP must not be asserted for at least 100 ns after leaving ZZ state.

Sequential Non-burst Read and Write Timing Diagram

CLK

ADSP

ADSC

ADDR

A

B

C

D

ADV

CE1

WE

OE

DQ

Q(A)

Q(B)

Q(C)

Q(D)

READS

NOTES:

1. ADSP = high, ADSC = low, ADV = high, CE1 = low.

2. H ≥ VIH, L ≤ VIL.

E

F

G

H

Q(E)

Q(F)

Q(G)

Q(H)

WRITES

14

Rev 1.1 - 5/01/98

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