C167CS-LM データシートの表示（PDF） - Infineon Technologies
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C167CS-LM Datasheet PDF : 517 Pages
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C167CS
Derivatives
Introduction
1.2
Summary of Basic Features
The C167CS is an improved representative of the Infineon family of full featured 16-bit
single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5/16.5
million instructions per second) with high peripheral functionality and means for power
reduction.
Several key features contribute to the high performance of the C167CS (the indicated
timings refer to a CPU clock of 25/33 MHz).
High Performance 16-bit CPU with Four-Stage Pipeline
• 80/60 ns minimum instruction cycle time, with most instructions executed in 1 cycle
• 400/300 ns multiplication (16-bit × 16-bit), 800/600 ns division (32-bit/16-bit)
• Multiple high bandwidth internal data buses
• Register based design with multiple variable register banks
• Single cycle context switching support
• 16 MBytes linear address space for code and data (Von Neumann architecture)
• System stack cache support with automatic stack overflow/underflow detection
Control Oriented Instruction Set with High Efficiency
• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits
for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access
Integrated On-Chip Memory
• 3 KByte internal RAM for variables, register banks, system stack and code
• 8 KByte on-chip high-speed XRAM for variables, user stack and code
• 32 KByte on-chip ROM (not for ROMless devices)
External Bus Interface
• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas
User’s Manual
1-4
V2.0, 2000-07
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