C8051F321 データシートの表示（PDF） - Unspecified

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C8051F321

Full Speed USB, 16k ISP FLASH MCU Family

Unspecified 

C8051F320/1

Table 16.2. Minimum SDA Setup and Hold Times .............................................................181

Figure 16.5. SMB0CF: SMBus Clock/Configuration Register .............................................182

Figure 16.6. SMB0CN: SMBus Control Register .................................................................184

Table 16.3. Sources for Hardware Changes to SMB0CN ....................................................185

Figure 16.7. SMB0DAT: SMBus Data Register ...................................................................186

Figure 16.8. Typical Master Transmitter Sequence...............................................................187

Figure 16.9. Typical Master Receiver Sequence ...................................................................188

Figure 16.10. Typical Slave Receiver Sequence ...................................................................189

Figure 16.11. Typical Slave Transmitter Sequence ...............................................................190

Table 16.4. SMBus Status Decoding....................................................................................191

17. UART0 .................................................................................................................................193

Figure 17.1. UART0 Block Diagram.....................................................................................193

Figure 17.2. UART0 Baud Rate Logic ..................................................................................194

Figure 17.3. UART Interconnect Diagram ............................................................................195

Figure 17.4. 8-Bit UART Timing Diagram ...........................................................................195

Figure 17.5. 9-Bit UART Timing Diagram ...........................................................................196

Figure 17.6. UART Multi-Processor Mode Interconnect Diagram .......................................197

Figure 17.7. SCON0: Serial Port 0 Control Register.............................................................198

Figure 17.8. SBUF0: Serial (UART0) Port Data Buffer Register .........................................199

Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ...........200

Table 17.2. Timer Settings for Standard Baud Rates Using an External Oscillator.............200

Table 17.3. Timer Settings for Standard Baud Rates Using an External Oscillator.............201

Table 17.4. Timer Settings for Standard Baud Rates Using an External Oscillator.............201

Table 17.5. Timer Settings for Standard Baud Rates Using an External Oscillator.............202

Table 17.6. Timer Settings for Standard Baud Rates Using an External Oscillator.............202

18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........................................203

Figure 18.1. SPI Block Diagram............................................................................................203

Figure 18.2. Multiple-Master Mode Connection Diagram ....................................................206

Figure 18.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...206

Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....206

Figure 18.5. Master Mode Data/Clock Timing......................................................................208

Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................................209

Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................................209

Figure 18.8. SPI0CFG: SPI0 Configuration Register............................................................210

Figure 18.9. SPI0CN: SPI0 Control Register ........................................................................211

Figure 18.10. SPI0CKR: SPI0 Clock Rate Register ..............................................................212

Figure 18.11. SPI0DAT: SPI0 Data Register ........................................................................213

Figure 18.12. SPI Master Timing (CKPHA = 0)...................................................................214

Figure 18.13. SPI Master Timing (CKPHA = 1)...................................................................214

Figure 18.14. SPI Slave Timing (CKPHA = 0) .....................................................................215

Figure 18.15. SPI Slave Timing (CKPHA = 1) .....................................................................215

Table 18.1. SPI Slave Timing Parameters............................................................................216

19. TIMERS ..............................................................................................................................217

Figure 19.1. T0 Mode 0 Block Diagram................................................................................218

Figure 19.2. T0 Mode 2 Block Diagram................................................................................219

Rev. 1.1

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