C8051F363 データシートの表示（PDF） - Silicon Laboratories

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C8051F363

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

C2CK/RST

VDD

GND

C2D

Reset

Power-On

Reset

Supply

Monitor

Power

Net

Debug / Programming

Hardware

CIP-51 8051

Controller Core

32/16 kB ISP FLASH

Program Memory

256 Byte RAM

1 kB XRAM

2-cycle 16 by 16 Multiply

and Accumulate

XTAL1

XTAL2

System Clock Setup

External

Oscillator

Internal

Oscillator

Clock

Multiplier

Low Frequency Oscillator

Port I/O Configuration

Digital Peripherals

UART0

Timers 0, 1,

2, 3

PCA/WDT

Priority

Crossbar

Decoder

SMBus

SPI

Crossbar Control

Port 0

Drivers

Port 1

Drivers

Port 2

Drivers

SFR

Bus

External Memory

Interface

Control

P0 / P4

Port 3

Drivers

Address

Data

P2 / P3 / P4

Port 4

P1

Drivers

VREF

VDD

Analog Peripherals

CP0

+

-

10-bit P4.4

CP1

+

IDAC

-

VREF

2 Comparators

10-bit

200 ksps

ADC

C8051F360 only

A

AIN0–AIN16

M

VDD

U

Temp

X

Sensor

Figure 1.1. C8051F360/3 Block Diagram

P0.0

P0.1/TX

P0.2/RX

P0.3/VREF

P0.4/IDA0

P0.5/XTAL1

P0.6/XTAL2

P0.7/CNVSTR

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6/C2D

20

Rev. 1.0

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