C8051F380 データシートの表示（PDF） - Silicon Laboratories

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C8051F380

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

C2CK/RST

VDD

VREG

GND

D+

D-

VBUS

C2D

Reset

Power-On

Reset

Supply

Monitor

Power

Net

Voltage

Regulators

Debug / Programming

Hardware

CIP-51 8051

Controller Core

64/32/16 kB ISP FLASH

Program Memory

256 Byte RAM

4/2 kB XRAM

XTAL1

XTAL2

System Clock Setup

External Oscillator

Internal Oscillator

Clock

Recovery

Low Freq.

Oscillator

USB Peripheral

Full / Low

Speed

Transceiver

Controller

1 kB RAM

SFR

Bus

Port I/O Configuration

Digital Peripherals

UART0

UART1

Timers 0, 1,

2, 3, 4, 5

PCA/WDT

Priority

Crossbar

Decoder

SMBus0

SMBus1

SPI

Crossbar Control

Port 0

Drivers

Port 1

Drivers

Port 2

Drivers

Port 3

Drivers

Analog Peripherals

VREF

VDD

VREF

CP0

+

-

CP1

+

-

2 Comparators

10-bit

500 ksps

ADC

A

VDD

M

U

Temp

X

Sensor

AIN0 - AIN20

Figure 1.2. C8051F381/3/5/7/C Block Diagram

P0.0

P0.1

P0.2/XTAL1

P0.3/XTAL2

P0.4

P0.5

P0.6/CNVSTR

P0.7/VREF

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0/C2D

Rev. 1.4

19

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