CDB5364(2007) データシートの表示（PDF） - Cirrus Logic

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CDB5364
(Rev.:2007)

114 dB, 192 kHz, 4-Channel A/D Converter

Cirrus Logic 

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING

Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF

Parameter

CCLK Clock Frequency

RST Rising Edge to CS Falling

CS Falling to CCLK Edge

CS High Time Between Transmissions

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

(Note 1)

(Note 2)

(Note 2)

Symbol

fsck

tsrs

tcss

tcsh

tscl

tsch

tdsu

tdh

tpd

tr1

tf1

tr2

tf2

Min

0

20

20

1.0

66

66

40

15

-

Max

6.0

-

50

25

100

Notes:

1. Data must be held for sufficient time to bridge the transition time of CCLK.

2. For fsck <1 MHz

CS5364

Units

MHz

ns

μs

ns

RST

tsrs

CS

tcss

tsch

tscl

tcsh

tr2

CCLK

tf2

tdsu

tdh

CDIN

tpd

CDOUT

Figure 6. SPI Timing

18

DS625F2

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