MAX121C データシートの表示（PDF） - Maxim Integrated

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MAX121C

308ksps ADC with DSP Interface and 78dB SINAD

Maxim Integrated 

MAX121

308ksps ADC with DSP Interface and 78dB SINAD

Maximum Clock Rate tor Serial Interface

The maximum serial clock rate depends upon the mini-

mum setup time required by the receiving processor’s

serial data input and the ADC’s maximum clock-to-data

delay. The MAX121 allows two fundamentally different

methods of clocking data into the processor. In the first

clocking method, CLKIN is both the input clock to the

MAX121 and the serial clock for the processor. With the

second method, CLKIN is the input clock for the MAX121

while SCLK is the serial clock for shifting data into the

processor (see Figure 11).

The first method would generally be used with simple

serial-interface standards (such as SPI) where the pro-

cessor does not support asynchronous data transfers.

The maximum clock-to-data delay would be tCD + tSC.

For this case, calculate the maximum serial clock rate

with the following formula:

fCLKIN = (1/2) x 1/(tSU + tCD + tSC)

where tSU is the minimum data setup time required at the

processor serial data input, tCD is the maximum CLKIN­

to-SCLK delay of the MAX121, and tSC is the maximum

SCLK-to-SDATA delay for the MAX121.

The second type of interface is intended for applications

where the processor supports asynchronous data trans-

fers. The SCLK output of the MAX121 drives the serial

clock of the processor, eliminating the tCD term from the

above equation and allowing the use of faster clocks. For

this case, calculate the maximum serial clock rate with the

following formula:

fCLKIN = (1/2) x 1/(tSU + tSC)

where the variables are as defined above.

Motorola SPI Serial Interface (CPOL = 0, CPHA = 1)

Figure 13 shows the MAX121 and processor interface

connections required to support the SPl standard. Figure

12 shows the SPI interface timing diagram. For SPI inter-

faces, the processor SS input should be pulled high, to

configure the processor as the master. An I/O port from

the processor drives the MAX121 CONVST (mode 1) or

CS (mode 2) low to control the conversion starts. The

SCK output of the processor will drive the CLKIN of the

MAX121. The MISO I/O of the processor is driven by the

SDATA output of the MAX121.

The SPI standard requires that all data transfers occur

in blocks of 8 bits, but the MAX121 outputs data in

16-bit blocks. Therefore, two 1-byte read operations are

required to receive the full 14 data bits from the MAX121.

A conversion is initiated by driving the processor I/O port

low. Next, a write operation must be performed by the

processor to activate the serial clock and read the first 8

bits of data from the MAX121.

The MAX121 output data transitions on the rising edge of

the clock. The processor reads data on the falling edge of

the clock (CPHA = 1). This provides one half clock cycle

to satisfy the minimum setup and hold time requirement

of the processor data input. The maximum clock rate for

SPI interfaces is 2MHz.

The first byte of data read by the processor will consist of

a leading zero followed by the 7 MSBs of data. A second

write operation should then be initiated to read the second

byte of data, which contains the 7 LSBs of conversion

data followed by a trailing zero. To minimize errors due to

the droop of the MAX121 internal T/H, limit the maximum

time delay between the conversion start and the end of

the second read operation to no more than 160µs.

CLKIN

tCD

tCD

SCLK

(INVCLK = VDD)

tSC*

SDATA FSTRT

SFRM

* tSS CAN BE POSITIVE OR NEGATIVE

Figure 11. Timing Diagram for Serial Data

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