CS43L21 データシートの表示（PDF） - Cirrus Logic

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CS43L21

Low Power, Stereo Digital to Analog Converter

Cirrus Logic 

4.3.8

CS43L21

On-Chip Charge Pump

An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual

rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large,

DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency

(bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage

drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply,

VSS_HP, and may result in clipping.

The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor

attached, at a default switching frequency. This frequency may be adjusted in the control port registers.

Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor con-

nected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple in-

duced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the

typical connection diagrams in Figure 1 on page 9 or Figure 2 on page 10 for the recommended capacitor

values for the charge pump circuitry.

Software

Controls:

“Charge Pump Frequency (Address 21h)” on page 53.

4.4 Serial Port Clocking

The D/A serial audio interface port operates either as a slave or master. It accepts externally generated

clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in

master mode.

The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,

Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked

into or out of the device.

The SPEED and MCLKDIV2 software control bits or the M/S and MCLKDIV2 stand-alone control pins, con-

figure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode.

The value on the M/S pin is latched immediately after powering up in Hardware Mode.

Software

Control:

Hardware

Control:

, “DAC Control (Address 09h)” on page 42.

Pin

“M/S” pin 29

“MCLKDIV2” pin 2

Setting

47 kΩ Pull-down

47 kΩ Pull-up

LO

HI

Selection

Slave

Master

No Divide

MCLK is divided by 2 prior

to all internal circuitry.

28

DS723A1

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