CS4811 データシートの表示（PDF） - Cirrus Logic

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CS4811

Fixed Function Multi-Effects Audio Processor

Cirrus Logic 

CS4811

dress byte. The slave address consists of the 4 most

significant bits set to 1010, the following 3 bits cor-

responding to the device select bits, A2, A1 and A0

set to 000 and the last bit (R/W) set to 0. Following

this, a 2-byte EEPROM starting address of 0x0000

is sent to the EEPROM. The 2-byte EEPROM

starting address uses only the lowest 13 bits and

sets the highest 3 bits to zero. To begin reading

from the EEPROM, the CS4811 sends another start

condition followed by a read preamble. The read

preamble is identical to the write preamble except

for the state of the R/W bit. The CS4811 then auto-

matically clocks out sequential bytes from the EE-

PROM until the last byte has been received. These

bytes include initialization and configuration data

for the device along with the application firmware

code. After the last byte, the CS4811 initiates a stop

condition and begins program execution. At this

point, the serial control port becomes inactive and

cannot be accessed.

3.6 Resets

Full chip reset can only be achieved by asserting

the RST pin. With RST asserted, the chip enters

low power mode during which the control port,

CODEC and Audio Processor are reset, all registers

are returned to their default values and the DAC

outputs are muted. The RST pin should be asserted

during power-up until the power supplies have

reached steady state.

If the supply voltage drops below 4 Volts, the CO-

DEC is reset, the DAC outputs are muted and the

Audio Processor automatically executes a soft re-

set.

Upon exit from a CODEC reset, the Audio Proces-

sor restarts the application code and the CODEC

performs the following procedure:

• The CODEC resynchronizes.

• The DAC outputs unmute.

SCL

0 1 2 3 4 5 6 7 8 9 10 16 17 18 19 25 26 27 28 29 30 31 32 33 34 35 36 37

CHIP ADDRESS (WRITE)

MEMORY ADDRESS

CHIP ADDRESS (READ)

DATA

SDA

1 0 1 0 A2 A1 A0 0

00 0

00 0

1 0 1 0 A2 A1 A0 1

70

ACK

ACK

ACK

ACK

START

START

DATA +n

70

NO

ACK STOP

Figure 10. Control Port Timing, I2C Master Mode Self-Boot

DS486PP2

15

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