CS4922 データシートの表示（PDF） - Cirrus Logic
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CS4922 Datasheet PDF : 33 Pages
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CS4922
SWITCHING CHARACTERISTICS - CONTROL PORT (I2C MODE) (TA = 25 °C;
VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF)
Parameter
Symbol Min Max Units
I2C® Mode (CS=1)
(Note 10)
SCK/SCL Clock Frequency
(slow mode)
(fast mode)
fscl
100 kHz
400
Bus Free Time Between Transmissions
tbuf
4.7
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
µs
Clock Low Time
slow
fast
tlow
4.7
µs
1.2
Clock High Time
slow
fast
thigh
4.0
µs
1.0
SDA Setup Time to SCK/SCL Rising
SDA Hold Time from SCK/SCL Falling
Rise Time of Both SDA and SCK/SCL
Fall Time of Both SDA and SCK/SCL
Time from SCK/SCL Falling to CS4920 ACK
Time from SCK/SCL Falling to SDA
Valid During READ Operation
tsud
250
ns
(Note 11) thdd
0
µs
(Note 12)
tr
50
ns
tf
300
ns
tsca
40
ns
tscsdv
40
ns
Time from SCK/SCL Rising to REQ Rising
Hold Time for REQ from SCK/SCL Rising
Rise Time for REQ
Fall Time for REQ
Setup Time for Stop Condition
(Note 13) tscrh
200
ns
(Note 14) tscrl
0
ns
(Note 13)
trr
50
ns
(Note 14)
trf
20
ns
tsusp
4.7
µs
Notes: 10. Use of I2C® bus compatible interface requires a license from Philips.
11. Data must be held for sufficient time to bridge the 300ns transition time of SCK/SCL.
12. This rise time is shorter than the I2C specifications recommend, please refer to the section on SCP
communications for more information.
13. REQ will only go HIGH if there is no data in the SCPOUT register at the rising edge of SCL/SCK during
a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 kΩ CL = 20pF.
14. if REQ went HIGH as indicated in Note 13 then REQ will hold HIGH at least until the next rising edge of
SCK/SCL. If data is in the SCPOUT register at this time REQ will go active LOW again. This condition
should be treated as a new READ process. The address and R/W should be sent again following a new
START condition.
10
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