CS5371A データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5371A

Low-power, High-performance ΔΣ Modulators

Cirrus Logic 

CS5371A CS5372A

DIGITAL CHARACTERISTICS (CONT.)

Parameter

Master Clock Input

MCLK Frequency

MCLK Period

MCLK Duty Cycle

MCLK Rise Time

MCLK Fall Time

MCLK Jitter (in-band or aliased in-band)

MCLK Jitter (out-of-band)

Master Sync Input

MSYNC Setup Time to MCLK Falling

MSYNC Period

MSYNC Hold Time after MCLK Falling

MDATA Output

MDATA Output Bit Rate

MDATA Output Bit Period

MDATA Output One’s Density Range

Full-scale Output Code

Symbol Min

Typ Max

(Note 20) fCLK

-

2.048

-

(Note 20) tmclk

-

488

-

(Note 9) MCLKDC

40

-

60

(Note 9) tRISE

-

-

50

(Note 9) tFALL

-

-

50

(Note 9) MCLKIBJ

-

-

300

(Note 9) MCLKOBJ

-

-

1

(Note 9, 21) tmss

20

122

-

(Note 9, 21) tmsync

40

976

-

(Note 9, 21) tmsh

20

122

-

(Note 9)

(Note 22)

fmdata

tmdata

MDATOD

MDATFS

-

-

14

0xA2EBE0

512

1953

-

-

-

-

86

0x5D1420

Unit

MHz

ns

%

ns

ns

ps

ns

ns

ns

ns

kbits/s

ns

%

Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power-

down state.

21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant

(t0) is on the next MCLK rising edge.

22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter.

DS748F2

11

Share Link: