CS61581-IL(2005) データシートの表示（PDF） - Cirrus Logic
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CS61581-IL Datasheet PDF : 37 Pages
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CS61581
Figure 12 shows the timing relationships for data
transfers when CLKE = 0. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th clock
cycle. When CLKE = 0, data bit D7 is held valid
until the rising edge of the 17th clock cycle. SDO
goes high-impedance after CS goes high or at the
end of the hold period of data bit D7.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in applica-
tions where the host processor has a bidirectional
I/O port.
An address/command byte, shown in Figure 12,
points to addresses 0x10 through 0x15 (address
0x10 shown), and precedes a data byte. The first bit
of the address/command byte determines whether a
read or a write is requested. The next six bits con-
tain the address. The last bit is ignored. Data to the
internal registers is input on the eight clock cycles
immediately following the address/command byte.
The register bit assignments are shown in Table 3.
CS
SCLK
SDI
SDO
CLKE = 0
R/W 0 0 0 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7
Address/Command Byte
Data Input/Output
D0 D1 D2 D3 D4 D5 D6 D7
Figure 12. Input/Output Timing (showing address 0x10)
7
6
5
4
3
2
1
Control Register 1 LH
(CR2.0 = 0) (CR1LH)
Control Register 1 SH
(CR2.0 = 1) (CR1SH)
Control Register 2 LH
(CR2.0 = 0) (CR2LH)
Control Register 2 SH
(CR2.0 = 1) (CR2SH)
Equalizer Gain
(EQGAIN)
RAM Address
(RAM)
Control Register 3
(CR3)
Data Pattern Error Count
(DPEC)
TAOS
TAOS
AIS
AIS
X
MSB
QRSS-
PATH
MSB
LLOOP RLOOP
LLOOP RLOOP
RAMPLSE MATCHZ
RAMPLSE MATCHZ
X
X
-
E1_LH
-
-
RST_
QERR
-
LB02
LEN2
LB01
LEN1
CODER
TAZ
LEN0
LOOPDN LOOPUP RPWDN
RSVD RCODER TCODER
EQ4
EQ3
EQ2
-
-
-
QDET
INS_QERR
QSYNC
TEST
-
-
-
NLOOP
RSVD
TxHIZ
TxHIZ
EQ1
-
QGEN
-
0
LOS
LOS
SH/LH
SH/LH
EQ0
LSB
TEST
LSB
ADDR
0x10 R/W
0x10 R/W
0x11 R/W
0x11 R/W
0x12 R
0x13 R/W
0x14 R/W
0x15 R
Table 3. Register Map
DS211PF1P8
17
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