CS61581-IP データシートの表示（PDF） - Cirrus Logic

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CS61581-IP

T1/E1 Universal Line Interface

Cirrus Logic 

CS61581

2.16 Control Register 2 SH: Address 0x11

7 (MSB)

AIS

6

RAMPLSE

5

MATCHZ

4

RSVD

3

RCODER

2

TCODER

1

TxHIZ

0 (LSB)

SH/LH

AIS

Alarm Indication Signal.

AIS = 1 when an all ones pattern is present at the receiver. This bit is reset to “0” by the first

read occurring after the AIS condition has cleared.

An interrupt will occur when AIS is present unless a “1” is written to AIS disabling the interrupt.

RAMPLSE

When RAMPLSE = 1, output pulse shapes are determined by the codes in the internal RAM.

MATCHZ

Matched Impedance Drive

When MATCHZ = 1 the output impedance is automatically set to match the impedance of a

standard T1 or E1 line.

A 1:1.5 transformer should be used when MATCHZ = 1, and a 1:2 transformer should be used

when MATCHZ = 0. (See Figures 15 and 16.)

RSVD

Reserved. Set to “0” for normal operation.

RCODER

Receive Decoder Enable

In Short Haul mode, when TNEG is held high, setting RCODER to “1” causes the received data

to be B8ZS/HDB3 decoded (depends on T1 or E1 pulse shape selection). When RCODER is

set to “0” the decoders are set for AMI only. This bit has precedence over the external pin.

TCODER

Transmit Encoder Enable

In Short Haul mode, when TNEG is held high, when TCODER = 1 the transmitter B8ZS/HDB3

encoders are enabled (depends on T1 or E1 pulse shape selection). When TCODER is set to

“0” the decoders are set for AMI only. This bit has precedence over the external pin.

TxHIZ

Transmitter High Impedance

When TxHIZ = 1 the transmitter goes to a low-power, high-impedance state

SH/LH

Short Haul / Long Haul Select

When SH/LH = 0, the CS61581 is in the Long Haul mode.

When SH/LH = 1, the CS61581 is in the Short Haul mode.

SH/LH controls the functions of the bits of Control Register 1 (address 0x10), and Control Reg-

ister 2 (address 0x11).

2.17 Equalizer Gain (EQGAIN): Address 0x12

7 (MSB)

6

X

X

5

4

3

2

1

0 (LSB)

X

EQ4

EQ3

EQ2

EQ1

EQ0

EQ[4:0]

The receive equalizer gain settings are broken down into 20 segments and provided at the five

LSBs of this register, EQ4 - EQ0. 00001 corresponds to -2 dB, 10100 corresponds to -40 dB.

The three MSBs are don’t cares.

2.18 RAM Address (RAM): Address 0x13

7 (MSB)

RAM.7

6

RAM.6

5

RAM.5

4

RAM.4

3

RAM.3

2

RAM.2

1

RAM.1

0 (LSB)

RAM.0

RAM[7:0]

The RAM address pointer for the arbitrary waveform memory;

a special write procedure must be followed to write the waveform RAM.

DS211PP8

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