CS7666 データシートの表示（PDF） - Cirrus Logic
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CS7666 Datasheet PDF : 42 Pages
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CS7666
Master Reset Register (00h)
7
6
5
4
3
2
1
0
res
res
res
res
res
res
res
MR
Reserved
W
MR
Setting bit MR0 to logic high will initiate a CS7666 master reset equivalent to executing an ex-
ternal reset using the RESET pin. All registers will be placed in their default state, and the down-
load of any external EPROM present on the secondary I2C bus will be initiated. The bit is self-
cleared.
Status Register (01h)
7
res
Reserved
6
P4BYTE
R
5
INTERP
R
4
HIZENB
R
3
INITACT
R
2
I2CBUSY
R
1
NODEV
R
0
EVNFLD
R
EVNFLD
NODEV
I2CBUSY
INITACT
Logic high indicates even field of interline-transfer CCD. Logic low indicates odd field of inter-
line-transfer CCD. This bit provides a course means of synchronizing to the field rate.
Logic high indicates that the addressed slave device on the secondary I2C bus did not respond.
Logic high indicates that the CS7666 secondary I2C master is busy accessing the addressed
slave device.
Logic high indicates the CS7666 master is busy initializing registers from the external I2C
EPROM on the secondary I2C bus (if present).
HIZENB
Pin 63 status.
INTERP
Pin 54 status.
P4BYTE
Pin 1 status.
PIN I/O Control (02h)
7
6
5
4
3
2
1
0
res
res
res
res
res
UV_ENB
FIELDOUT
PLLOUT
Reserved
R/W
R/W
R/W
PLLOUT
Logic high enables the PLL clock output to the CS7615 (pin 51). This pin was a NC on the
CS7665.
FIELDOUT
Logic high changes FIELD (pin 62) from an input to an output pin. Default is input.
UV_ENB
Logic high replaces FIELD with a U/V clock.
Digital Gain Register (03h)
7
6
5
res
res
res
Reserved
4
DG4
3
DG3
2
DG2
R/W
1
DG1
0
DG0
DG[4:0]
Controls the digital gain applied to the Y (Luminance) signal after the RGB to YCrCb converter
block. The range of gains are from 0 to 31/8 in increments of 1/8. A gain of 0, indicates no bright-
ness.
DS302PP1
21
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