CXA2153 データシートの表示（PDF） - Sony Semiconductor
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CXA2153 Datasheet PDF : 24 Pages
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CXA2153S
Description of Operation
1. Sharpness function
The RGB signals input to Pins 5, 7 and 10 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The
high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is
controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its
amplitude clipped by a limiter circuit and is then added to the R, G and B signals.
SHP GAIN = 0 (HEX)
or SHP OFF = 1
No sharpness component
100%
SHP GAIN = F (HEX)
100%
25ns
(T SW = 1)
50ns
(T SW = 2)
100ns
(T SW = 3)
Section not sent to RGB output because of the limiter
Limiter level = 30% (Typ.)
10%
∗ The output level when RIN = GIN = BIN = 0.7Vp-p
is set to 100%.
2. VBLK synchronous DAC refresh system
The VBLK signal is removed from the composite BLK signal which has been input to Pin 14, and the data for
each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data
is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the
microcomputer is timing-free. Set the width of the V blanking pulse which is input to Pin 14 to 300µs or more.
(See the next page)
3. Gamma correction function
Using the output obtained when 700mVp-p RGB signals are input as a reference (100 [IRE]), the ±9 [IRE]
(GAMMA1) and ±20 [IRE] (GAMMA2) waveforms can be corrected at the 15 [IRE] and 60 [IRE] inflection points,
respectively.
The polarity switching gain can be controlled separately for each point, enabling correction broken at two
points. The I2C bus controls the polarity switching and gain correction.
GAMMA1
GAMMA2
100 [IRE]
+20 [IRE]
–20 [IRE]
100 [IRE]
+9 [IRE]
–9 [IRE]
0
15 [IRE]
100 [IRE] 0
– 21 –
60 [IRE]
100 [IRE]
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