ICX412_ データシートの表示（PDF） - Sony Semiconductor

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ICX412_

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Sony Semiconductor 

Chart-4 Vertical Direction Timing Chart

VD

HD

SUB

V1A

V1B

V2

V3A

V3B

V4

CCD OUT

PBLK

CLPOB

Wide CLPOB

CLPDM

ID/EXP

WEN

54

72 2

High-speed

E sweep block

D

E

Frame shift block

6

4

MODE

AF2 mode

21

Applicable CCD image sensor

• ICX412

54

72 2

21

High-speed

E

sweep block

D

E Frame shift block

6

4

∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.

∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

∗ 116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block.

∗ VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units.

High-speed sweep block starts from 68H. However, in this case, NTSC equivalent pattern frame rate is 0.5ck longer than 1/120s.

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