CY14B101LA データシートの表示（PDF） - Cypress Semiconductor
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CY14B101LA Datasheet PDF : 24 Pages
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PRELIMINARY
CY14B101LA, CY14B101NA
Hardware STORE Cycle
Parameters
Description
tDHSB
tPHSB
tSS [29, 30]
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
Soft Sequence Processing Time
20 ns
Min Max
20
15
100
25 ns
Min Max
25
15
100
Switching Waveforms
Write latch set
Figure 14. Hardware STORE Cycle[23]
HSB (IN)
HSB (OUT)
DQ (Data Out)
tPHSB
tDELAY
tSTORE
tHHHD
tLZHSB
45 ns
Unit
Min Max
25 ns
15
ns
100 μs
RWI
Write latch not set
tPHSB
HSB (IN)
HSB (OUT)
RWI
tDELAY
tDHSB
tDHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
Address
CE
VCC
Figure 15. Soft Sequence Processing[29, 30]
Soft Sequence
tSS
Command
Address #1
tSA
Address #6
tCW
Soft Sequence
tSS
Command
Address #1
Address #6
tCW
Notes
29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
30. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-42879 Rev. *C
Page 15 of 24
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