M36W432BGZAT データシートの表示（PDF） - STMicroelectronics

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M36W432BGZAT

32 Mbit (2Mb x16, Boot Block) Flash Memory and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

STMicroelectronics 

M36W432TG, M36W432BG

SRAM OPERATIONS

There are five standard operations that control the

SRAM component. These are Bus Read, Bus

Write, Standby/Power-down, Data Retention and

Output Disable. A summary is shown in Table 2,

Main Operation Modes

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable, WS, is at VIH, Out-

put Enable, GS, is at VIL, Chip Enable, E1S, is at

VIL, Chip Enable, E2S, is at VIH, and Byte Enable

inputs, UBS and LBS are at VIL.

Valid data will be available on the output pins after

a time of tAVQV after the last stable address. If the

Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (tE1LQV, tE2HQV, or tGLQV) rath-

er than the address. Data out may be indetermi-

nate at tE1LQX, tE2HQX and tGLQX, but data lines

will always be valid at tAVQV (see Table 23, Table

23, Figures 17 and 18, SRAM Read AC Character-

istics).

Write. Write operations are used to write data to

the SRAM. The SRAM is in Write mode whenever

WS and E1S are at VIL, and E2S is at VIH. Either

the Chip Enable inputs, E1S and E2S, or the Write

Enable input, WS, must be deasserted during ad-

dress transitions for subsequent write cycles.

A Write operation is initiated when E1S is at VIL,

E2S is at VIH and WS is at VIL. The data is latched

on the falling edge of E1S, the rising edge of E2S

or the falling edge of WS, whichever occurs last.

The Write cycle is terminated on the rising edge of

E1S, the rising edge of WS or the falling edge of

E2S, whichever occurs first.

If the Output is enabled (E1S=VIL, E2S=VIH and

GS=VIL), then WS will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must

be taken to avoid bus contention in this type of op-

eration. The Data input must be valid for tDVWH be-

fore the rising edge of Write Enable, for tDVE1H

before the rising edge of E1S or for tDVE2L before

the falling edge of E2S, whichever occurs first, and

remain valid for tWHDX, tE1HAX or tE2LAX (see Table

24, SRAM Write AC Characteristics, Figures 20,

21, 22 and 23).

Standby/Power-Down. The SRAM component

has a chip enabled power-down feature which in-

vokes an automatic standby mode (see Table 23,

SRAM Read AC Characteristics, Figure 19, SRAM

Standby AC Waveforms). The SRAM is in Standby

mode whenever either Chip Enable is deasserted,

E1S at VIH or E2S at VIL. It is also possible when

UBS and LBS are at VIH.

Data Retention. The SRAM data retention per-

formance as VDDS goes down to VDR are de-

scribed in Table 25, SRAM Low VDDS Data

Retention Characteristic, and Figure 24, SRAM

Low VDDS Data Retention AC Waveforms, E1S or

UBS / LBS Controlled. In E1S controlled data reten-

tion mode, the minimum standby current mode is

entered when E1S ≥ VDDS – 0.2V and E2S ≤ 0.2V

or E2S ≥ VDDS – 0.2V. In E2S controlled data re-

tention mode, minimum standby current mode is

entered when E2S ≤ 0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable, GS, is at VIH

with Write Enable, WS, at VIH.

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