M36W432TG, M36W432BG
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled
A0-A17
DQ0-DQ15
tAVQV
tAXQX
DATA VALID
tAVAV
VALID
DATA VALID
Note: E1S = Low, E2S = High, GS = Low, UBS and/or LBS = High, WS = High.
AI07942
Figure 18. SRAM Read AC Waveforms, GS Controlled
tAVAV
A0-A17
tE1LQV
VALID
E1S
tE1LQX
tE2HQV
E2S
tE2HQX
tBLQV
UBS, LBS
tBLQX
tGLQV
GS
DQ0-DQ15
tGLQX
tGHQZ
DATA VALID
tE1HQZ
tE2LQZ
tBHQZ
AI07943
Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1S, UBS and LBS going Low.
Figure 19. SRAM Standby AC Waveforms
E1S
E2S
tPU
IDD
50%
tPD
AI07913
41/66