M59MR032C データシートの表示（PDF） - STMicroelectronics

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M59MR032C

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M59MR032C, M59MR032D

STATUS REGISTER BITS

P/E.C. status is indicated during execution by Data

Polling on ADQ7, detection of Toggle on ADQ6

and ADQ2, or Error on ADQ5 bits. Any read at-

tempt within the Bank being modified and during

Program or Erase command execution will auto-

matically output these five Status Register bits.

The P/E.C. automatically sets bits ADQ2, ADQ5,

ADQ6 and ADQ7. Other bits (ADQ0, ADQ1 and

ADQ4) are reserved for future use and should be

masked (see Table 18). Read attempts within the

bank not being modified will output array data.

Toggle bits ADQ6 and ADQ2 are affected by G

and/or E cycles regardless of the bank in which

these cycles refer to. This means that toggle bits

are in a state that depends on the amount of ac-

cesses to both banks and not only to the bank

where erasing or programming is on going. Status

Register Bits must be accessed according to the

device configuration (see Figure 4).

Data Polling Bit (ADQ7). When Programming

operations are in progress, this bit outputs the

complement of the bit being programmed on

ADQ7. In case of a double word program opera-

tion, the complement is done on ADQ7 of the last

word written to the command interface, i.e. the

data written in the fifth cycle. During Erase opera-

tion, it outputs a ’0’. After completion of the opera-

tion, ADQ7 will output the bit last programmed or

a ’1’ after erasing. Data Polling is valid and only ef-

fective during P/E.C. operation, that is after the

fourth W pulse for programming or after the sixth

W pulse for erase. It must be performed at the ad-

dress being programmed or at an address within

the block being erased. See Figure 17 for the Data

Polling flowchart and Figure 15 for the Data Polling

waveforms. ADQ7 will also flag the Erase Sus-

pend mode by switching from ’0’ to ’1’ at the start

of the Erase Suspend. In order to monitor ADQ7 in

the Erase Suspend mode an address within a

block being erased must be provided. For a Read

Operation in Suspend mode, ADQ7 will output ’1’

if the read is attempted on a block being erased

and the data value on other blocks. During Pro-

gram operation in Erase Suspend Mode, ADQ7

will have the same behavior as in the normal pro-

gram execution outside of the suspend mode.

Toggle Bit (ADQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read ADQ6 will output complementary

data. ADQ6 will toggle following toggling of either

G, or E when G is at VIL. The operation is complet-

ed when two successive reads yield the same out-

put data. The next read will output the bit last

programmed or a ’1’ after erasing. The toggle bit

ADQ6 is valid only during P/E.C. operations, that

is after the fourth W pulse for programming or after

the sixth W pulse for Erase. ADQ6 will be set to ’1’

if a Read operation is attempted on an Erase Sus-

pend block. When erase is suspended ADQ6 will

toggle during programming operations in a block

different from the block in Erase Suspend. Either

E or G toggling will cause ADQ6 to toggle. See

Figure 18 for Toggle Bit flowchart and Figure 16

for Toggle Bit waveforms.

Toggle Bit (ADQ2). This toggle bit, together with

ADQ6, can be used to determine the device status

during the Erase operations. During Erase Sus-

pend a read from a block being erased will cause

ADQ2 to toggle. A read from a block not being

erased will output data. ADQ2 will be set to ’1’ dur-

ing program operation. After erase completion and

if the error bit ADQ5 is set to ’1’, ADQ2 will toggle

if the faulty block is addressed.

Error Bit (ADQ5). This bit is set to ’1’ by the P/

E.C. when there is a failure of programming or

block erase, that results in invalid data in the mem-

ory block. In case of an error in block erase or pro-

gram, the block in which the error occurred or to

which the programmed data belongs, must be dis-

carded. Other Blocks may still be used. The error

bit resets after a Read/Reset (RD) instruction. In

case of success of Program or Erase, the error bit

will be set to ’0’.

Erase Timer Bit (ADQ3). This bit is set to ‘0’ by

the P/E.C. when the last block Erase command

has been entered to the Command Interface and it

is awaiting the Erase start. When the erase time-

out period is finished, ADQ3 returns to ‘1’, in the

range of 80µs to 120µs.

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