CY7C1021BN-15VC データシートの表示（PDF） - Cypress Semiconductor
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CY7C1021BN-15VC Datasheet PDF : 10 Pages
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Switching Characteristics[5] Over the Operating Range (continued)
Parameter
Write Cycle[8]
Description
7C10211B-10
Min. Max.
tWC
tSCE
tAW
tHA
tSA
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
10
8
7
0
0
5
0
3
5
7
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
CY7C1021BN
CY7C10211BN
7C1021B-12
Min. Max.
7C1021B-15
Min. Max. Unit
12
15
ns
9
10
ns
8
10
ns
0
0
ns
0
0
ns
6
8
ns
0
0
ns
3
3
ns
6
7
ns
8
9
ns
DATA VALID
ADDRESS
tRC
CE
OE
BHE, BLE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tHZOE
DATA VALID
tHZCE
tHZBE
HIGH
IMPEDANCE
tPD
50%
IICCCC
IISSBB
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
Document #: 001-06494 Rev. *A
Page 5 of 10
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