A386DX データシートの表示（PDF） - Intel
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A386DX Datasheet PDF : 139 Pages
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Intel386TM DX MICROPROCESSOR
cal space of the machine 4 Gbytes (232 bytes) If a
maximum sized segment is used (limit e
FFFFFFFFH) it should be Dword aligned (i e the
least two significant bits of the segment base should
be zero) This will avoid a segment limit violation (ex-
ception 13) caused by the wrap around In Real Ad-
dress Mode the maximum segment size is fixed at
64 Kbytes (216 bytes)
The six segments addressable at any given moment
are defined by the segment registers CS SS DS
ES FS and GS The selector in CS indicates the
current code segment the selector in SS indicates
the current stack segment the selectors in DS ES
FS and GS indicate the current data segments
2 3 5 Segment Descriptor Registers
The segment descriptor registers are not program-
mer visible yet it is very useful to understand their
content Inside the Intel386 DX a descriptor register
(programmer invisible) is associated with each pro-
grammer-visible segment register as shown by Fig-
ure 2-4 Each descriptor register holds a 32-bit seg-
ment base address a 32-bit segment limit and the
other necessary segment attributes
When a selector value is loaded into a segment reg-
ister the associated descriptor register is automati-
cally updated with the correct information In Real
Address Mode only the base address is updated
directly (by shifting the selector value four bits to the
left) since the segment maximum limit and attributes
are fixed in Real Mode In Protected Mode the base
address the limit and the attributes are all updated
per the contents of the segment descriptor indexed
by the selector
Whenever a memory reference occurs the segment
descriptor register associated with the segment be-
ing used is automatically involved with the memory
reference The 32-bit segment base address be-
comes a component of the linear address calcula-
tion the 32-bit limit is used for the limit-check opera-
tion and the attributes are checked against the type
of memory reference requested
2 3 6 Control Registers
The Intel386 DX has three control registers of 32
bits CR0 CR2 and CR3 to hold machine state of a
global nature (not specific to an individual task)
These registers along with System Address Regis-
ters described in the next section hold machine
state that affects all tasks in the system To access
the Control Registers load and store instructions
are defined
CR0 Machine Control Register (includes 80286
Machine Status Word)
CR0 shown in Figure 2-5 contains 6 defined bits for
control and status purposes The low-order 16 bits
of CR0 are also known as the Machine Status Word
MSW for compatibility with 80286 Protected Mode
LMSW and SMSW instructions are taken as special
aliases of the load and store CR0 operations where
only the low-order 16 bits of CR0 are involved For
compatibility with 80286 operating systems the In-
tel386 DX LMSW instructions work in an identical
fashion to the LMSW instruction on the 80286 (i e It
only operates on the low-order 16-bits of CR0 and it
ignores the new bits in CR0 ) New Intel386 DX oper-
ating systems should use the MOV CR0 Reg in-
struction
The defined CR0 bits are described below
PG (Paging Enable bit 31)
the PG bit is set to enable the on-chip paging
unit It is reset to disable the on-chip paging
unit
R (reserved bit 4)
This bit is reserved by Intel When loading CR0
care should be taken to not alter the value of
this bit
31
24 23
16 15
87
0
P
G
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
T
S
EM
MP
P
E
CR0
X
Y
MSW
NOTE 0 indicates Intel reserved Do not define SEE SECTION 2 3 10
Figure 2-5 Control Register 0
12
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