CY7C1021D-10ZSXA データシートの表示（PDF） - Cypress Semiconductor
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CY7C1021D-10ZSXA Datasheet PDF : 17 Pages
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CY7C1021D
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
■ Temperature Ranges:
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Pin and Function Compatible with CY7C1021B
■ High Speed
❐ tAA = 10 ns
■ Low Active Power
❐ ICC = 80 mA at 10 ns
■ Low CMOS Standby Power
❐ ISB2 = 3 mA
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Independent Control of Upper and Lower Bits
■ Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and
44-pin TSOP II Packages
Functional Description
The CY7C1021D is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected. The input and output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during
a write operation (CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
The CY7C1021D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
A3
64K x 16
RAM Array
A2
A1
A0
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05462 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 19, 2013
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