CY7C1021D-10ZSXA データシートの表示（PDF） - Cypress Semiconductor
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CY7C1021D-10ZSXA Datasheet PDF : 17 Pages
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CY7C1021D
Switching Characteristics
Over the Operating Range
Parameter [8]
Description
Read Cycle
tpower [9]
VCC(typical) to the first access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z [10]
OE HIGH to High Z [10, 11]
CE LOW to Low Z [10]
CE HIGH to High Z [10, 11]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle [12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [10]
WE LOW to High Z [10, 11]
Byte Enable to End of Write
-10 (Industrial /
Automotive-A)
Unit
Min
Max
100
–
s
10
–
ns
–
10
ns
3
–
ns
–
10
ns
–
5
ns
0
–
ns
–
5
ns
3
–
ns
–
5
ns
0
–
ns
–
10
ns
–
5
ns
0
–
ns
–
5
ns
10
–
ns
7
–
ns
7
–
ns
0
–
ns
0
–
ns
7
–
ns
6
–
ns
0
–
ns
3
–
ns
–
5
ns
7
–
ns
Notes
8.
Test
and
conditions
30-pF load
assume signal
capacitance.
transition
time
of
3
ns
or
less,
timing
reference
levels
of
1.5
V,
input
pulse
levels
of
0
to
3.0
V,
and
output
loading
of
the
specified
IOL/IOH
9. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tsHtaZtOeE. , tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
12. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
a LOW to HIGH transition on any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal
that terminates the write.
Document Number: 38-05462 Rev. *M
Page 7 of 17
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