UPD703014AF1-XXX-EA6 データシートの表示（PDF） - NEC => Renesas Technology
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UPD703014AF1-XXX-EA6 Datasheet PDF : 48 Pages
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µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VDD
–0.5 to +4.6
V
AVDD
–0.5 to +4.6
V
BVDD
–0.5 to +4.6
V
AVSS
–0.5 to +0.5
V
Input voltage
Clock input voltage
Analog input voltage
Analog reference input voltage
BVSS
VI1
VI2
VK
VIAN
AVREF
Note 1
Note 2
X1, XT1, VDD = 2.7 to 3.6 V
Note 3 (AVDD)
AVREF
–0.5 to +0.5
V
–0.5 to VDD + 0.5Note 4
V
–0.5 to BVDD + 0.5Note 4
V
–0.5 to VDD + 1.0Note 4
V
–0.5 to AVDD + 0.5Note 4
V
–0.5 to AVDD + 0.5Note 4
V
Output current, low
IOL
Per pin
4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Total for P50 to P57, P60 to P65
25
mA
Output current, high
IOH
Per pin
–4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
–25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
–25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
–25
mA
Output voltage
Total for P50 to P57, P60 to P65
VO1
Note 1, VDD = 2.7 to 3.6 V
VO2
Note 2, BVDD = 2.7 to 3.6 V
–25
mA
–0.5 to VDD + 0.5Note 4
V
–0.5 to BVDD + 0.5Note 4
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins.
2. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins.
3. Ports 7, 8, and their alternate-function pins.
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
18
Data Sheet U14526EJ2V0DS00
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