CY7C1325G(2004) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1325G Datasheet PDF : 16 Pages
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PRELIMINARY
CY7C1325G
Thermal Resistance[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
TQFP Package
TBD
TBD
BGA Package
TBD
TBD
Unit
°C/W
°C/W
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 3.3V
TQFP Package
5
5
5
BGA Package Unit
5
pF
5
pF
7
pF
3.3V I/O Test Load
OUTPUT
3.3V
Z0 = 50Ω
OUTPUT
RL = 50Ω
5 pF
INCLUDING
VT = 1.5V
(a)
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
2.5V
Z0 = 50Ω
OUTPUT
RL = 50Ω
5 pF
INCLUDING
VT = 1.25V
JIG AND
(a)
SCOPE
R = 317Ω
R = 351Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1ns
90%
10%
≤ 1ns
(b)
R = 1667Ω
R =1538Ω
(b)
(c)
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1ns
(c)
90%
10%
≤ 1ns
Switching Characteristics Over the Operating Range [14, 15]
133 MHz
117 MHz
100 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the first Access[10]
Min. Max. Min. Max. Min. Max. Unit
1
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
8.5
10
ns
2.5
3.0
4.0
ns
2.5
3.0
4.0
ns
tCDV
Data Output Valid After CLK Rise
6.5
7.5
8.0 ns
tDOH
tCLZ
Data Output Hold After CLK Rise
Clock to Low-Z[11, 12, 13]
2.0
2.0
2.0
ns
0
0
0
ns
Shaded areas contain advance information.
Notes:
9. Tested initially and after any design or process change that may affect these parameters.
10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05518 Rev. *A
Page 8 of 16
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