AD5533ABC-1 データシートの表示（PDF） - Analog Devices

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AD5533ABC-1

32-Channel Infinite Sample-and-Hold

Analog Devices 

AD5533

APPLICATION CIRCUITS

AD5533 in a Typical ATE System

The AD5533 infinite sample-and-hold is ideally suited for use

in automatic test equipment. Several ISHAs are required to

control pin drivers, comparators, active loads, and signal timing.

Traditionally, sample-and-hold devices with droop were used in

this application. These required refreshing to prevent the voltage

from drifting.

The AD5533 has several advantages: no refreshing is required,

there is no droop, pedestal error is eliminated, and there is no

need for extra filtering to remove glitches. Overall, a higher level

of integration is achieved in a smaller area, see Figure 13.

ISHA

ISHA

ISHA

ACTIVE

LOAD

PARAMETRIC

MEASUREMENT SYSTEM BUS

UNIT

STORED

DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND

DELAY

TIMING

DRIVER

ISHA

FORMATTER

ISHA

COMPARE

REGISTER

ISHAs

SYSTEM BUS

COMPARATOR

ISHA

ISHA

DUT

Figure 13. AD5533 in an ATE System

Typical Application Circuit

The AD5533 can be used to set up voltage levels on 32 channels

as shown in the circuit below. An AD780 provides the 3 V refer-

ence for the AD5533 and for the AD5541 16-bit DAC. A simple

3-wire interface is used to write to the AD5541. Because the

AD5541 has an output resistance of 6.25 kΩ (typ), the time taken

to charge/discharge the capacitance at the VIN Pin is significant.

Hence an AD820 is used to buffer the DAC output. Note that it

is important to minimize noise on VIN and REFIN when laying out

this circuit.

AVCC

AVCC DVCC VSS

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5533 is mounted should be designed so that the analog and

digital sections are separated and confined to certain areas of the

board. If the AD5533 is in a system where multiple devices

require an AGND-to-DGND connection, the connection should

be made at one point only. The star ground point should be

established as close as possible to the device. For supplies with

multiple pins (VSS, VDD, and AVCC), it is recommended to tie

those pins together. The AD5533 should have ample supply

bypassing of 10 µF in parallel with 0.1 µF on each supply located

as close to the package as possible, ideally right up against the

device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance (ESR)

and effective series inductance (ESI), like the common ceramic

types that provide a low impedance path to ground at high frequen-

cies, to handle transient currents due to internal logic switching.

The power supply lines of the AD5533 should use as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals, such as

clocks, should be shielded with digital ground to avoid radiating

noise to other parts of the board and should never be run near

the reference inputs. A ground line routed between the DIN and

SCLK lines will help reduce crosstalk between them (not required

on a multilayer board as there will be a separate ground plane but

separating the lines will help).

Note it is essential to minimize noise on VIN and REFIN lines.

Particularly for optimum ISHA performance, the VIN line must

be kept noise-free. Depending on the noise performance of the

board, a noise filtering capacitor may be required on the VIN line.

If this capacitor is necessary, then for optimum throughput it may

be necessary to buffer the source which is driving VIN. Avoid cross-

over of digital and analog signals. Traces on opposite sides of the

board should run at right angles to each other. This reduces the

effects of feedthrough through the board. A microstrip technique is

by far the best but not always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground plane while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid

flexing the package and to avoid a point load on the surface of

the package during the assembly process.

CS

DIN

SCLK

VDD

AD5541* AD820

REF

VIN

AD5533*

OFFS_IN

OFFS_OUT

REFIN

VOUT 0–31

AD780*

VOUT

SCLK DIN SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. Typical Application Circuit

REV. A

–15–

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