AD5532-5 データシートの表示（PDF） - Analog Devices
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AD5532-5 Datasheet PDF : 20 Pages
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AD5532
SERIAL INTERFACE
Table 4.
Parameter1, 2
f3
CLKIN
t1
t2
t3
t4
t5
t6
t7
t8 4
t94
t10
t11
t12 5
Limit at TMIN, TMAX (A Version)
14
28
28
15
50
10
5
5
20
60
400
400
7
t1
SCLK
1
2
3
t3
t2
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
4
5
Conditions/Comments
SCLK frequency
SCLK high pulse width
SCLK low pulse width
SYNC falling edge to SCLK falling edge setup time
SYNC low time
DIN setup time
DIN hold time
SYNC falling edge to SCLK rising edge setup time for read back
SCLK rising edge to DOUT valid
SCLK falling edge to DOUT high impedance
10th SCLK falling edge to SYNC falling edge for read back
24th SCLK falling edge to SYNC falling edge for DAC mode write
SCLK falling edge to SYNC falling edge setup time for read back
6
7
8
9
10
SYNC
DIN
SCLK
SYNC
DIN
SCLK 10
SYNC
DOUT
t4
t5
t6
MSB
LSB
Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)
t1
1
2
3
4
5
21
22
23
24
1
t3
t2
t4
t5
t11
t6
MSB
t7
1
t12
t1
2
3
t2
Figure 5. 24-Bit Write (DAC Mode)
4
5
6
7
8
9
LSB
10
11
12
13
14
t10
t4
t8
t9
MSB
LSB
Figure 6. 14-Bit Read (Both Readback Modes)
1 See Figure 4, Figure 5, and Figure 6.
2 Guaranteed by design and characterization, not production tested.
3 In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.
4 These numbers are measured with the load circuit of Figure 3.
5 SYNC should be taken low while SCLK is low for read back.
Rev. D | Page 7 of 20
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