CY7C1363B データシートの表示（PDF） - Cypress Semiconductor
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CY7C1363B Datasheet PDF : 34 Pages
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CY7C1361B
CY7C1363B
CY7C1363B: Pin Definitions (continued)
Name
TQFP
(3-Chip
Enable)
TQFP
(2-Chip
Enable)
BGA
(2-Chip
Enable)
BWA,BWB
93,94
93,94
L5,G3
GW
88
88
H4
BWE
CLK
CE1
87
87
M4
89
89
K4
98
98
E4
CE2
97
97
B2
CE3[2]
92
–
–
OE
86
86
F4
ADV
83
83
G4
ADSP
84
84
A4
fBGA
(3-Chip
Enable)
B5,A4
B7
A7
B6
A3
B3
A6
B8
A9
B9
I/O
Description
Input-
Synchronous
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of
CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW[A:B] and BWE).
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
Input-
Clock
Clock Input. Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
Input-
Synchronous
Input-
Synchronous
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to
select/deselect the device. ADSP is ignored
if CE1 is HIGH.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to
select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to
select/deselect the device.
Input-
Asynchronous
Output Enable, asynchronous input,
active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
OE is masked during the first clock of a read
cycle when emerging from a deselected
state.
Input-
Synchronous
Advance Input signal, sampled on the
rising edge of CLK. When asserted, it
automatically increments the address in a
burst cycle.
Input-
Synchronous
Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW. When asserted LOW,
addresses presented to the device are
captured in the address registers. A[1:0] are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH.
Document #: 38-05302 Rev. *B
Page 10 of 34
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