CY7C4201-15AXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4201-15AXC Datasheet PDF : 19 Pages
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Switching Waveforms (continued)
Full Flag Timing
NO Write
WCLK
D0 –D8
tSKEW1[15]
FF
tWFF
NO Write
tDS
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
NO Write
tSKEW1[15]
DATA Write
tWFF
tWFF
DATA Write
WEN1
WEN2
(if applicable)
RCLK
REN1,
REN2
tENS
tENH
tENS
tENH
OE
Q0 –Q8
LOW
tA
DATA IN OUTPUT REGISTER
Programmable Almost Empty Flag Timing
WCLK
tCLKH
WEN1
tCLKL
tENS tENH
DATA Read
tA
NEXT DATA Read
WEN2
(if applicable)
PAE
RCLK
tENS tENH
tSKEW2[22]
Note
23
tPAE
N + 1 WORDS
INFIFO
Note
24
tPAE
REN1,
REN2
tENS
tENS tENH
Notes:
22. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
23. PAE offset = n.
24. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
Document #: 38-06016 Rev. *C
Page 12 of 19
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