CY7C4241-15AXC データシートの表示（PDF） - Cypress Semiconductor

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CY7C4241-15AXC

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

Switching Waveforms (continued)

Programmable Almost Full Flag Timing

WCLK

tCLKH

WEN1

tCLKL

tENS tENH

Note

25

WEN2

(if applicable)

PAF

RCLK

tENS tENH

FULL − M+1 WORDS

IN FIFO

Note

26

tPAF

FULL − M WORDS

IN FIFO[27]

tSKEW2[28]

tPAF

REN1,

REN2

tENS

tENS tENH

Write Programmable Registers

WCLK

tCLKH

WEN2/LD

WEN1

D0 –D8

tCLK

tCLKL

tENS

tENS

tENH

tDS

tDH

PAE OFFSET

LSB

PAE OFFSET

MSB

PAF OFFSET

LSB

PAF OFFSET

MSB

Notes:

25. If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW.

26. PAF offset = m.

27. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,

4096 – m words for CY7C4241, 8192 – m words for CY7C4251.

28. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Document #: 38-06016 Rev. *C

Page 13 of 19

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