CYRF69313-40LTXC データシートの表示（PDF） - Cypress Semiconductor
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CYRF69313-40LTXC Datasheet PDF : 80 Pages
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CYRF69313
Table 2. SPI Transaction Format
Bit#
7
6
Bit Name DIR
INC
Byte 1
[5:0]
Address
CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard-architecture microprocessor. Five registers
control the primary operation of the CPU core. These registers
are affected by various instructions, but are not directly
accessible through the register space by the user.
Table 3. CPU Registers and Register Names
Register
Flags
Program Counter
Accumulator
Stack Pointer
Index
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows for direct
addressing of the full eight Kbytes of program memory space.
[7:0]
Data
Byte 1+N
The Accumulator Register (CPU_A) is the general purpose
register that holds the results of instructions that specify any of
the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by the
SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable
interrupts. The user cannot manipulate the Supervisory State
status bit [3]. The flags are affected by arithmetic, logic, and shift
operations. The manner in which each flag is changed is
dependent upon the instruction being executed (for example,
AND, OR, XOR). See Table 20 on page 17.
Document Number: 001-66503 Rev. *C
Page 11 of 80
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