CYRF69313-40LFXC データシートの表示（PDF） - Cypress Semiconductor

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CYRF69313-40LFXC

Programmable Radio-on-Chip LPstar

Cypress Semiconductor 

CYRF69313

Functional Block Overview

All the blocks that make up the PRoC LPstar are presented here.

2.4 GHz Radio

The radio transceiver is a dual conversion low IF architecture

optimized for power and range/robustness. The radio employs

channel matched filters to achieve high performance in the

presence of interference. An integrated Power Amplifier (PA)

provides up to 0 dBm transmit power, with an output power

control range of 30 dB in six steps. The supply current of the

device is reduced as the RF output power is reduced.

Table 1. Internal PA Output Power Step Table

PA Setting

6

5

4

3

2

1

0

Typical Output Power (dBm)

0

–5

–10

–15

–20

–25

–30

Frequency Synthesizer

Before transmission or reception may commence, it is necessary

for the frequency synthesizer to settle. The settling time varies

depending on channel; 25 fast channels are provided with a

maximum settling time of 100 s.

The ‘fast channels’ (<100 s settling time) are every third

frequency, starting at 2400 MHz up to and including 2472 MHz

(for example, 0,3,6,9…….69 and 72).

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding

and decoding, SOP generation and reception and CRC16

generation and checking, and EOP detection and length field.

Data Rates and Data Transmission Modes

The SoC supports two different data transmission modes:

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

■ In DSSS mode eight bits (8DR, 32 chip) are encoded in each

derived code symbol transmitted, resulting in effective

250 Kbps data rate.

32 chip Pseudo Noise (PN) codes are supported. The two data

transmission modes apply to the data after the SOP. In particular

the length, data, and CRC16 are all sent in the same mode. In

general, DSSS reduce packet error rate in any environment.

Link Layer Modes

The CYRF69313 IC device supports the following data packet

framing features:

SOP

Packets begin with a two-symbol SoP marker. If framing is

disabled then an SOP event is inferred whenever two successive

correlations are detected. The SOP_CODE_ADR code used for

the SOP is different from that used for the “body” of the packet,

and if desired may be a different length. SOP must be configured

to be the same length on both sides of the link.

Length

Length field is the first eight bits after the SOP symbol, and is

transmitted at the payload data rate. An EoP condition is inferred

after reception of the number of bytes defined in the length field,

plus two bytes for the CRC16.

CRC16

The device may be configured to append a 16-bit CRC16 to each

packet. The CRC16 uses the USB CRC polynomial with the

added programmability of the seed. If enabled, the receiver

verifies the calculated CRC16 for the payload data against the

received value in the CRC16 field. The starting value for the

CRC16 calculation is configurable, and the CRC16 transmitted

may be calculated using either the loaded seed value or a zero

seed; the received data CRC16 is checked against both the

configured and zero CRC16 seeds.

CRC16 detects the following errors:

■ Any one bit in error

■ Any two bits in error (irrespective of how far apart, which

column, and so on)

■ Any odd number of bits in error (irrespective of the location)

■ An error burst as wide as the checksum itself

Figure 2 shows an example packet with SOP, CRC16 and

lengths fields enabled.

Figure 2. Example Default Packet Format

Preamble N*16us

2nd Framing Symbol*

Preamble SOP1

SOP2

Length

<== P a y l o a d ==>

1st Framing Symbol*

Packet length 1 Byte Period

CRC 16

*Note: 32 us

Document Number: 001-66503 Rev. *C

Page 7 of 80

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