CYRF69313 データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CYRF69313 Datasheet PDF : 80 Pages
| |||
CYRF69313
drain output, CMOS/TTL inputs, and CMOS output with up to five
pins that support programmable drive strength of up to 50 mA
sink current. GPIO Port 1 features four pins that interface at a
voltage level of 3.3 volts. Additionally, each I/O pin can be used
to generate a GPIO interrupt to the microcontroller. Each GPIO
port has its own GPIO interrupt vector with the exception of GPIO
Port 0. GPIO Port 0 has three dedicated pins that have
independent interrupt vectors (P0.3–P0.4).
Power-on Reset
The power-on reset (POR) circuit detects logic when power is
applied to the device, resets the logic to a known state, and
begins executing instructions at Flash address 0x0000. When
power falls below a programmable trip voltage, it generates reset
or may be configured to generate interrupt. The Watchdog timer
can be used to ensure the firmware never gets stalled in an
infinite loop.
Power Management
The device draws its power supply from the USB Vbus line. The
Vbus supplies power to the MCU function, which has an internal
3.3 V regulator. This 3.3 V is supplied to the radio function via
P1.2 after proper filtering as shown in Figure 3.
Figure 3. Power Management From Internal Regulator
1 ohm
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
P1.2
Vbus
VDD_MICRO
0.1µF
CYRF69313
Timers
The free-running 16-bit timer provides two interrupt sources: the
programmable interval timer with 1 s resolution and the
1.024 ms outputs. The timer can be used to measure the
duration of an event under firmware control by reading the timer
at the start and at the end of an event, then calculating the
difference between the two values.
USB Interface
The MCU function includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with three
endpoints.
Low Noise Amplifier (LNA) and Received Signal
Strength Indication (RSSI)
The gain of the receiver may be controlled directly by clearing
the AGC EN bit and writing to the low noise amplifier (LNA) bit of
the RX_CFG_ADR register. When the LNA bit is cleared, the
receiver gain is reduced by approximately 20 dB, allowing
accurate reception of very strong received signals (for example
when operating a receiver very close to the transmitter). An
additional 20 dB of receiver attenuation can be added by setting
the Attenuation (ATT) bit; this allows data reception to be limited
to devices at very short ranges. Disabling AGC and enabling
LNA is recommended unless receiving from a device using
external PA.
The RSSI register returns the relative signal strength of the
on-channel signal power.
When receiving, the device may be configured to automatically
measure and store the relative strength of the signal being
received as a 5-bit value. When enabled, an RSSI reading is
taken and may be read through the SPI interface. An RSSI
reading is taken automatically when the start of a packet is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI register, allowing the
background RF energy level on any channel to be easily
measured when RSSI is read when no signal is being received.
A new reading can occur as fast as once every 12 s.
SPI Interface
The SPI interface between the MCU function and the radio
function is a 3-wire SPI Interface. The three pins are MOSI
(Master Out Slave In), SCK (Serial Clock), SS (Slave Select).
There is an alternate 4-wire MISO Interface that requires the
connection of two external pins. The SPI interface is controlled
by configuring the SPI Configure Register (SICR Address:
0x3D).
Three-Wire SPI Interface
The radio function receives a clock from the MCU function on the
SCK pin. The MOSI pin is multiplexed with the MISO pin.
Bidirectional data transfer takes place between the MCU function
and the radio function through this multiplexed MOSI pin. When
using this mode the user firmware should ensure that the MOSI
pin on the MCU function is in a high impedance state, except
when the MCU is actively transmitting data. Firmware must also
control the direction of data flow and switch directions between
MCU function and radio function by setting the SWAP bit [Bit 7]
of the SPI Configure Register. The SS pin is asserted prior to
initiating a data transfer between the MCU function and the radio
function. The IRQ function may be optionally multiplexed with the
MOSI pin; when this option is enabled the IRQ function is not
available while the SS pin is low. When using this configuration,
user firmware should ensure that the MOSI function on MCU
function is in a high impedance state whenever SS is high.
Document Number: 001-66503 Rev. *C
Page 9 of 80
Share Link: 