D950-CORE データシートの表示（PDF） - STMicroelectronics
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D950-CORE Datasheet PDF : 89 Pages
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D950-Core
Control registers
CCR:
Bits 0 to 12 are dedicated to the DCU (see Section 4.5.2).
BSC:
6-bit Barrel Shifter Control register. The BSC contains a 6-bit signed shift value
(2’s complement). If the value is positive (resp. negative), all shifts using the
BSC contents will provide a left (resp. right) shift. After reset, the BSC value is
0.
PSC:
6-bit Product Shift Control register. The PSC contains a 6-bit signed shift value.
If the value is positive (resp. negative) there will be a left (resp. right) shift on
the P-register. After reset, the PSC value is 0.
DCU0CR:
Bits 0 to 7 are copied from bits 0 to 7 of the STA register. Bit 10 is used for
clearing the lower part (bits 0 to 15) and sign extending bits 32 to 39 of the
accumulator when its higher part (bits 16 to 31) is loaded.
4.1.3 Multiplier
The D950-Core multiplier performs 16 x 16-bit multiplications with the following
implementations (see SL and SR bits of STA register):
SL LL SR LR
0
X
0
X
1
0
0
X
0
X
1
0
1
0
1
0
SL 1 SR X
SL X SR 1
Multiplication
Unsigned L-source
X
Unsigned R-source
Signed L-source
X
Unsigned R-source
Unsigned L-source
X
Signed R-source
Signed L-source
X
Signed R-source
Unsigned L0
X
Unsigned R-source
(dep on SR-bit)
or
Signed/Unsigned L-source
X
Signed/Unsigned R-source
Signed/Unsigned L-source
X
(depending on SL-bit)
Unsigned R0
or
Signed/Unsigned L-source
Signed/Unsigned R-source
The 16 or 32-bit operands, are provided by a subset of the register file and stored in L1/L0 and
R1/R0, and accessed through X and Y buses.
The multiplication is performed in one single instruction cycle and the result is loaded in the
32-bit P register. The product can be either integer or fractional (see I-bit of STA register).
Rounding of the product is explicitly defined by the multiplication instructions (see Section
5.4.2).
I
Product
0
Fractional L-source
X
Fractional R-source
1
Integer L-source
X
Integer R-source
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